Irvine, CA
vrushanganand2004@gmail.com
https://www.vrushanganand.com
https://www.github.com/vrushang1234
https://www.linkedin.com/in/vrushang-anand12/
A custom reinforcement learning powered process scheduler integrated into the Arch Linux kernel for adaptive, low-latency task scheduling.
From physical frames to virtual pages: transforming raw RAM into isolated address spaces.
EECS 159B senior design report on an FPGA-based HFT system combining hardware order matching with an on-chip TPU.
A universal instruction set architecture for ML/DL FPGA accelerators, driven from high-level Python libraries such as PyTorch.
